The present invention relates to flash memory devices.
In a flash memory device, a bad block refers to a block that could not be repaired although column repair was performed on the block. The number of bad blocks generally needs to be no more than 2% of the total blocks.
A bad block is detected at the time of a wafer test in the manufacturing process of a flash memory device. A memory block that is determined to be a bad block is disabled in hardware by cutting a block fuse in the middle of a path that enables a corresponding block. The block fuse, when cut, makes it impossible to enable the word line of a block, thus disabling an operation of the corresponding block.
FIG. 1 is a circuit diagram showing a block selection circuit employing a conventional block fuse. This drawing shows a part of a block selection circuit that outputs a block enable signal. A block selection circuit 110 selects a memory block 120 of a flash memory device. The block selection circuit 110 includes first to third NAND gates NA1 to NA3 and a fuse F. The block selection circuit 110 is generally included in an X decoder of a flash memory device.
The first NAND gate NA1 outputs input block addresses XA, XB, XC, and XD to a node a1. The block addresses XA, XB, XC, and XD are block addresses that are decoded using a row address. The row address is input together with a program or read operation command of a flash memory device.
The fuse F is connected between the first NAND gate NA1 and the node a1.
The output of the first NAND gate NA1 is decided by the block addresses XA, XB, XC, and XD (hereinafter, referred to as “XABCD”). When the block address XABCD is a high level, the first NAND gate NA1 outputs a low-level signal, thus making the node a1 a low level. Further, a control signal PGMPREb of a low level is input to the second NAND gate NA2, which in turn outputs a low-level signal. Accordingly, an enable signal is input to a block corresponding to the block address XABCD.
This block selection circuit is connected to each block. The block selection circuit is adapted to not input an enable signal to a block which is recognized as a bad block. The fuse F is cut for a bad block.
Further, the second NAND gate NA2 logically combines a signal level of the node a1 and the program control signal PGMPREb and outputs a result to a node a2. The third NAND gate NA3 logically combines a logic level of the node a2 and an enable signal EN and outputs a result to the node a3. The memory block 120 is selected according to the logic levels of node a2 and node a3.
FIG. 2 is a timing diagram of the circuit shown in FIG. 1. At a time when the program control signal PGMPREb of a low level and the enable signal EN of a high level are applied, the block address signal XABCD is input to the first NAND gate NA1.
Thus, a signal BLKWL to select a block is precharged to a high level. If a block is processed as a bad block and the fuse F is cut, the signal BLKWL shifts to a low level when the program control signal PGMPREb shifts to a high level. Consequently, a corresponding memory block 120 is disabled.
The block selection circuit 110 is an important element for the operation of a flash memory device. However, in order to reduce the size of a flash memory device, it would be desirable to reduce the size of the block selection circuit 110.